Fabrication of Metal/Graphene Hybrid Interconnects by Direct Graphene Growth and Their Integration Properties. (30th April 2018)

• Record Type: Journal Article
• Authors: Lee, Chang‐Seok; Shin, Keun Wook; Song, Hyun‐Jae; Park, Hyun; Cho, Yeonchoo; Im, Dong‐Hyun; Lee, Hyangsook; Lee, Jae‐Ho; Won, Jung Yeon; Chung, Jae Gwan; Kim, Changhyun; Byun, Kyung‐Eun; Lee, Eun‐Kyu; Kim, Yongsung; Ko, Wonhee; Lim, Han Jin; Park, Seongjun; Shin, Hyeon‐Jin
• Is Part Of: Advanced Electronic Materials. Volume 4:Number 6(2018)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-04-30
• Subjects: diffusion barriers -- direct graphene growth -- interconnects -- resistance -- Si process compatibility; Materials -- Electric properties -- Periodicals; Materials science -- Periodicals; Magnetic materials -- Periodicals; Electronic apparatus and appliances -- Periodicals; 537
• DOI: 10.1002/aelm.201700624
• Languages: English
• ISSNs: 2199-160X

Abstract

Abstract: Although high‐quality graphene can be produced on catalyst metals, their practical applications, especially Si technologies, are limited by the high‐temperature growth and the posttransfer process. A high‐performance system composed of W/nanocrystalline graphene (nc‐G)/TiN is realized for the long‐term downscaling of interconnect technology. The nc‐G is directly grown on noncatalytic TiN, up to 300 mm in diameter, at a low temperature of ≈560 °C, which is below the complementary metal‐oxide semiconductor integration temperature. The versatile roles of nc‐G in the interconnect are demonstrated: as a promoter of the preferential grain growth of the W layer, as a diffusion barrier to metal‐silicide formation, and as a proper adhesion layer with adjacent layers. Overall, a significant reduction (27%) in the resistance of the interconnect is achieved by the insertion of nc‐G between W and TiN. This work points to the possibility of practical graphene applications via direct nc‐G growth that is compatible with current Si technology. Abstract : Nanocrystalline graphene (nc‐G)‐inserted low‐resistance interconnects with 300 mm wafer‐scale are presented. A highly ordered nc‐G with a honeycomb lattice is directly grown on a TiN substrate, providing lower activation energy for W deposition. Furthermore, it has a strong potential to replace the highly‐resistive diffusion layer with stable adhesion. The entire process from nc‐G growth to interconnect integration is compatible with the requirements of current Si technology.