A 0.9-V, 4.4-mW CMOS LNA with wideband input match and high gain for UWB applications. Issue 3 (3rd July 2018) - Pandey, Sunil; Gawande, Tushar; Pathak, Abhijeet; Kondekar, Pravin Neminath
ABSTRACT: In this work, we explore a 3.1–10.6-GHz low-noise amplifier (LNA) which takes advantage of the dual-resonant matching technique for extension of input matching bandwidth. However, forward-body-bias technique is utilised in the design to operate on lower supply voltage. In the input section, a dual-resonant matching technique is used to extend the bandwidth from 3.1 to 10.6 GHz. The drain inductors are used at the drain node of MOSFETs M1  and M2  to enhance the gain  S 21 . However, inductor  L m  is considered between two stages for gain compensation in the mid-frequency region. The designed ultra-wide band (UWB) LNA results in an  S 21  of 18.1 ± 0.65 dB in the frequency range of 3.1–10.6 GHz. It dissipates 4.4 mW power by using a  V dd  = 0.9 V. The designed circuit is simulated with a standard 90 nm CMOS technology. The achieved input return loss  S 11  is less than −10 dB, while output return loss,   S 22, is approximately equal to −10 dB in the frequency range of 3.1–10.6 GHz. The noise figure (NF) is below 3.25 dB, and minimum NF (NFmin ) exists in the range of 1.36–2.97 dB for the desired band of interest.