A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance *Supported by the National Natural Science Foundation of China under Grant Nos 61404014 and 61405018, the Fundamental Research Funds for the Central Universities under Grant Nos CDJZR12160003 and 106112014CDJZR168801. (September 2015)

• Record Type: Journal Article
• Authors: Hu 胡, Sheng-Dong 盛东; Jin 金, Jing-Jing 晶晶; Chen 陈, Yin-Hui 银晖; Jiang 蒋, Yu-Yu 玉宇; Cheng 程, Kun 琨; Zhou 周, Jian-Lin 建林; Liu 刘, Jiang-Tao 江涛; Huang 黄, Rui 蕊; Yao 姚, Sheng-Jie 胜杰
• Is Part Of: Chinese physics letters. Volume 32:Number 9(2015:Sep.)
• Publication Date: 2015-09
• Subjects: 85.30.De -- 85.30.−z -- 85.30.Mn; Physics -- Periodicals; Electronic journals; 530.05
• DOI: 10.1088/0256-307X/32/9/098502
• Languages: English
• ISSNs: 0256-307X

Abstract

Abstract : A novel silicon-on-insulator (SOI) power metal-oxide-semiconductor field effect transistor with an interface-gate (IG SOI) structure is proposed, in which the trench polysilicon gate extends into the buried oxide layer (BOX) at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.