Common Mode Voltage Reduction Using 3D-SVPWM for 3-level CI-NPC Inverter with Hybrid Energy System. Issue 4 (25th February 2018)

• Record Type: Journal Article
• Authors: Ramasamy, Palanisamy; Krishnasamy, Vijayakumar
• Is Part Of: Electric power components and systems. Volume 46:Issue 4(2018)
• Page Start: 391
• Page End: 405
• Publication Date: 2018-02-25
• Subjects: Three dimensional Space Vector Pulse Width Modulation (3D-SVPWM) -- Transformerless CI-NPC -- Common Mode Voltage (CMV) -- Field Programmable Gate Array (FPGA) -- Nearest State Vector (NSV) -- Photovoltaic (PV) system; Electric machinery -- Periodicals; 621.3104205
• DOI: 10.1080/15325008.2018.1446198
• Languages: English
• ISSNs: 1532-5008

Abstract

Abstract: This paper elucidates Common Mode Voltage (CMV) reduction in transformerless 3-phase 3-level Coupled Inductor Neutral Point (CI-NPC) Clamped Inverter with Hybrid Energy System. The three dimensional Space Vector Pulse Width Modulation (3D-SVPWM) with Nearest State Vector (NSV) is implemented to reduce the CMV by proper selection of medium, large and small vectors in 3D cubic space region. This NSV scheme in addition to CMV reduction, reduces the capacitor voltage balancing issues and minimizes switching losses. The proposed control provides full utilization of dc link voltage with reduced harmonics. This 3-level CI-NPC inverter is energized by hybrid energy source which includes photovoltaic system and wind energy system. The results obtained for the proposed scheme through simulation and experimental setup is compared with the conventional 2D-SVPWM and 3D-SVPWM scheme. From the compared results it is evident that the proposed scheme reduces CMV to a larger extent than 2D and 3D-SVPWM control. The simulation and experimental results are verified using matlab-simulink and FPGA-Spartan-6 controller respectively.