Three novel single-stage full swing 3-input XOR. Issue 8 (3rd August 2018) - Vijaya Lakshmi, P.; Musala, Sarada; Srinivasulu, Avireni; Pal, Dipankar
ABSTRACT: In this paper, three novel designs for single-stage, 3-input XOR logic cells are proposed. The design uses either Transmission Gate (TG) or Pass Transistor (PT) on similar topologies. The proposed circuits are area and power efficient because minimum-sized transistors are used in ratioless realisations. At the output, the designs give strong logic-levels. The topologies have minimised delay because the critical path consists of only three minimum-sized transistors. The delay estimation is presented. The circuits are simple and layouts are easy to build. Further, rail-to-rail voltage-swing at the output ensures good driving capability even at low voltages and at high frequencies ranging up to 10 GHz with minimum transistor count. The proposed designs and other existing candidate designs are simulated in a pragmatic condition on Cadence 90 nm CMOS technology at various supply voltages ranging from +0.8 V to +1.2 V. The simulation results illustrate that the proposed designs have comparable delay time to most candidate designs while it outperform all of them on total power consumption and PDP. As expected, the TG-based design reports best performance while the PT-based design follow as closed second with better component economy and control input overload. An application of the proposed XORs in ripple carry adders confirms the functionality of the cells in circuit implementation.