Hardware solution for implementing the entire inverse IDCTs in HEVC decoder. Issue 8 (3rd August 2018)

• Record Type: Journal Article
• Authors: Nayeri, Hamid Reza; Zargari, Farzad
• Is Part Of: International journal of electronics. Volume 105:Issue 8(2018)
• Page Start: 1261
• Page End: 1272
• Publication Date: 2018-08-03
• Subjects: HEVC -- IDCT -- hardware implementation -- video coding; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2018.1440427
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: Video compression performance of High Efficiency Video Coding (HEVC) is about twice of H.264/AVC video compression standard. The improvement in coding efficiency in HEVC is achieved by considerable increase in the computational load compared to H.264/AVC which is substantially very computational intensive. One of the units in HEVC which has changed considerably compared to H.264/AVC is Integer Discrete Cosine Transform (IDCT) unit. IDCT in HEVC standard includes 32 × 32, 16 × 16, 8 × 8 and 4 × 4 transforms. In this paper, a hardware solution for implementing the entire inverse IDCTs in HEVC decoder is proposed. The proposed hardware has a resource-sharing pipelined architecture. As a result, the hardware resources and computation time for implementing inverse IDCTs in HEVC decoder are reduced. Synthesis results by using NanGate OpenPDK 45 nm library indicate that the proposed hardware can achieve 222 MHz clock rate and can achieve real-time decoding of 4096 × 3072 video sequences with 70 fps.