A Review on SEU Mitigation Techniques for FPGA Configuration Memory. Issue 2 (4th March 2018)

• Record Type: Journal Article
• Authors: Nidhin, T. S.; Bhattacharyya, Anindya; Behera, R. P.; Jayanthi, T.
• Is Part Of: IETE technical review. Volume 35:Issue 2(2018)
• Page Start: 157
• Page End: 168
• Publication Date: 2018-03-04
• Subjects: Configuration memory -- Error correction codes -- Fault tolerance -- Field programmable gate array -- Look-up-tables -- Partial reconfiguration -- Routing errors -- Single event upsets -- Scrubbing; Telecommunication -- Periodicals; Electronics -- Periodicals; Electronics; Telecommunication; Periodicals; 621.38
• DOI: 10.1080/02564602.2016.1265905
• Languages: English
• ISSNs: 0256-4602

Abstract

ABSTRACT: Single event upset (SEU) has become one of the major threats to dependable application development targeted at safety systems in field programmable gate arrays (FPGAs). This article briefly reviews the mitigation techniques for SEUs in the configuration memory of SRAM-based FPGAs, as the configuration memory is highly susceptible to SEUs. Various reconfiguration methods are reviewed and the main focus is given to partial reconfiguration with error correction codes and scrubbing. It also covers the algorithmic and architectural changes which prevent or mitigates SEUs in the configuration memory bits dedicated for routing resources and logic resources. The major techniques are compared based on their SEU mitigation capability, area overhead, and delay.