Optimizations in a high-performance conjugate gradient benchmark for IA-based multi- and many-core processors. (February 2016)

• Record Type: Journal Article
• Authors: Park, Jongsoo; Smelyanskiy, Mikhail; Vaidyanathan, Karthikeyan; Heinecke, Alexander; Kalamkar, Dhiraj D; Patwary, Md Mosotofa Ali; Pirogov, Vadim; Dubey, Pradeep; Liu, Xing; Rosales, Carlos; Mazauric, Cyril; Daley, Christopher
• Is Part Of: International journal of high performance computing applications. Volume 30:Number 1(2016:Spring)
• Page Start: 11
• Page End: 27
• Publication Date: 2016-02
• Subjects: High-performance conjugate gradient -- HPCG -- conjugate gradient -- Xeon Phi -- Gauss–Seidel -- multi-grid -- loop fusion -- directed acyclic graph -- task scheduling; High performance computing -- Periodicals; Supercomputers -- Periodicals; 004.1105
• DOI: 10.1177/1094342015593157
• Languages: English
• ISSNs: 1094-3420

Abstract

This paper presents optimizations in a high-performance conjugate gradient benchmark (HPCG) for multi-core Intel ® Xeon ® processors and many-core Xeon Phi™ coprocessors. Without careful optimization, the HPCG benchmark under-utilizes the compute resources available in modern processors due to its low arithmetic intensity and challenges in parallelizing the Gauss–Seidel smoother (GS). Our optimized implementation fuses GS with sparse matrix vector multiplication (SpMV) to address the low arithmetic intensity, overcoming the performance otherwise bound by memory bandwidth. This fusion optimization is progressively more effective in newer generation Xeon processors, demonstrating the usefulness of their larger caches for sparse matrix operations: Sandy Bridge, Ivy Bridge, and Haswell processors achieve 93%, 99%, and 103%, respectively, of the ideal performance with a constraint that matrices are streamed from memory. Our implementation also parallelizes GS using fine-grain level-scheduling, a method that has been believed not to scale with many cores. Our GS implementation scales with 60 cores in Xeon Phi coprocessors, for the finest level of the multi-grid pre-conditioner. At the coarser levels, we address the limited parallelism using block multi-color re-ordering, achieving 21 GFLOPS with one Xeon Phi coprocessor. These optimizations distinguish our HPCG implementation from the others that stream most of the data from main memory and rely on multi-color re-ordering for parallelism. Our optimized implementation has been evaluated in clusters with various configurations, and we find that low-diameter high-radix network topologies such as Dragonfly realize high parallelization efficiencies because of fast all-reduce collectives. In addition, we demonstrate that our optimizations not only benefit the HPCG dataset, which is based on a structured 3D grid, but also a wide range of unstructured matrices.