Nanolithography using thermal stresses. Issue 9 (29th January 2018)

• Record Type: Journal Article
• Authors: Purohit, Gangadhar; Deepak, ; Katiyar, Monica
• Is Part Of: RSC advances. Volume 8:Issue 9(2018)
• Page Start: 4928
• Page End: 4936
• Publication Date: 2018-01-29
• Subjects: Chemistry -- Periodicals; 540.5
• DOI: 10.1039/c8ra00278a
• Languages: English
• ISSNs: 2046-2069

Abstract

Abstract : A scalable nanolithography technique is demonstrated to realize nanogaps in Au electrodes using dissimilar thermal expansion coefficients of different layers. Abstract : Nanometer separation (nanogap) in electrodes is a fundamental requirement for several nanoscale devices having applications in nanoelectronics, nanophotonics, biosensing, nanoporous filters, healthcare and medical diagnostics. Most nanolithography techniques, other than extreme/deep ultraviolet lithography are serial processes, such as e-beam lithography, and therefore not scalable. We demonstrate fabrication of nanogaps in Au electrodes over a large area/wafer in parallel processing mode resulting in high throughput. The proposed technique requires tools that are already available in a typical semiconductor device fabrication facility. The concept involves designing a ceramic/metal multilayer structure which is heated to bring the ceramic under tensile stress, and as a result it develops cracks due to low fracture toughness of the ceramic. The feasibility of this idea was established by calculating thermal stresses in different multilayers when heated to a specified temperature level. At practical temperatures, below 500 °C, the developed tensile stresses are higher than the critical stress needed for fracture. Subsequent to separation in the ceramic layer at the desired location, the underlying metal layer can be wet etched leading to separation in the metal also. For electrode fabrication, a predefined notch in the multilayer structure is used to obtain the nanogap at the desired location. For experimental validation, SiO x /Au/Ti layers on glass and silicon are patterned in I-shaped electrodes using conventional optical lithography. After vacuum annealing and etching, nanogaps in Au electrodes are simultaneously formed across a large area substrate/wafer. The nanoscale gaps formed in the Au electrodes were inspected using optical microscopy, FE-SEM imaging and finally were verified using an electrical isolation test. We achieved nanogaps with dimensions of ∼150–300 nm in Au electrodes on glass substrates.