Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators. (14th December 2017)

• Record Type: Journal Article
• Authors: Boni, Andrea; Giuffredi, Luca; Pietrini, Giorgio; Magnanini, Alessandro; Tonelli, Matteo
• Is Part Of: International journal of circuit theory and applications. Volume 46:Number 4(2018)
• Page Start: 707
• Page End: 728
• Publication Date: 2017-12-14
• Subjects: analog‐to‐digital converters -- circuit modeling -- electronic noise -- harmonic‐distortion -- sigma‐delta modulator -- switched‐capacitor circuit; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2436
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐ μ W power consumption at 1.2‐V supply. Abstract : A behavioral model for SC‐SD modulators, suitable for power‐driven design and optimization, is presented. By means of an accurate model of the settling error and noise of the integrator, a global power minimization is achieved. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator.