Design and application of multi-stage reconfigurable signal processing flow on FPGA. (February 2015)

• Record Type: Journal Article
• Authors: Wu, Juhong; Yang, Dong; Chen, Zengping
• Is Part Of: Computers & electrical engineering. Volume 42(2015)
• Page Start: 1
• Page End: 11
• Publication Date: 2015-02
• Subjects: Reconfigurable computing -- Run-time reconfiguration -- Signal processing flow -- Electronic reconnaissance -- Multi-function; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2014.12.001
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: In this paper, we focus on the reconfiguration of complex, intensive and sequential signal processing systems and propose a Multi-Stage Reconfigurable Signal Processing Flow (MSRSPF). The signal processing flow is partitioned into a number of stages which are connected with unified interfaces. With the combination of staged processing flow, the whole system can work at multiple modes with diverse functions and switch to a more suitable mode quickly according to the change of application requirements. As an application case, we introduce the usage of MSRSPF in passive signal reconnaissance. The reconnaissance system based on MSRSPF is flexible and adaptable to the electromagnetic environment, and can get the electronic information from different views with more reliability. The performance testing results show that MSRSPF supports multiple hardware logic and has a good reconfigurability with time overhead no more than a few seconds.