Thermal stress probing the channel-length modulation effect of nano n-type FinFETs. (April 2018) - Tuan, Fu-Yuan; Chen, Chii-Wen; Wang, Mu-Chun; Liao, Wen-Shiang; Wang, Shea-Jue; Fan, Shou-Kong; Lan, Wen-How
Abstract: The 3D FinFETs deed provide the impressive gate controllability, especially in drive speed of transistors. However, this advantage relatively brings some drawbacks in channel length modulation (CLM) causing the difficulty in device model establishment. In this work, besides the study of n-type FinFETs in CLM effect, the previous study in 2D HK/MG nMOSFETs at room temperature is also referred and discussed with 3D FinFETs. The influence to the CLM effect at low gate bias is more apparent, speculating the quality of surface channel contributing the depletion width near drain site. The depletion width is usually influenced by raised temperature. And the CLM effect is gradually moved from the low-field dominated to the mid-field as the temperature increased at short-channel device no matter what the V T implant energy is, but not suitable to the others. Graphical abstract: Highlights: The basic electrical characterization of Si-based n-type FinFETs with SiON gate dielectric was demonstrated. The channel-length reduction related to the gate bias and temperature effect is illustrated. The comparison of channel-length reduction between 28 nm HK/MG devices and FinFETs at room temperature is done. The V T implant energies impacting the channel-length reduction were analyzed. According to the sensed data, the low gate bias seems to provide the more contribution to the CLM effect.