Wire Optimization and Delay Reduction for High‐Performance on‐Chip Interconnection in GALS Systems. Issue 4 (August 2017)

• Record Type: Journal Article
• Authors: Oh, Myeong‐Hoon; Kim, Young Woo; Kim, Hag Young; Kim, Young‐Kyun; Kim, Jin‐Sung
• Is Part Of: ETRI journal. Volume 39:Issue 4(2017)
• Page Start: 582
• Page End: 591
• Publication Date: 2017-08
• Subjects: High‐performance interconnection -- Current mode circuit -- Asynchronous protocol -- Delay insensitive -- CSL; Telecommunication -- Periodicals; Electronics -- Periodicals; Electronics; Telecommunication; Periodicals; Periodicals; 621.38205
• DOI: 10.4218/etrij.17.0116.0052
• Languages: English
• ISSNs: 1225-6463

Abstract

Abstract : To address the wire complexity problem in large‐scale globally asynchronous, locally synchronous systems, a current‐mode ternary encoding scheme was devised for a two‐phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current‐mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current‐mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25‐μm CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10‐mm wire. They also reduce the power‐delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.