10‐Bit 200‐MS/s Current‐Steering DAC Using Data‐Dependant Current‐Cell Clock‐Gating. Issue 1 (1st February 2013) - Yang, Byung‐Do; Seo, Bo‐Seok
Abstract : This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with VDD =1.2 V. Its area is 0.21 mm 2 . It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively.