5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣ Modulator Using Single Operational Amplifier and Single Feedback DAC. Issue 2 (1st April 2016)

• Record Type: Journal Article
• Authors: Cho, Young‐Kyun; Park, Bong Hyuk; Kim, Choul‐Young
• Is Part Of: ETRI journal. Volume 38:Issue 2(2016)
• Page Start: 217
• Page End: 226
• Publication Date: 2016-04-01
• Subjects: ΔΣ modulator -- single operational amplifier resonator -- second‐order loop filter; Telecommunication -- Periodicals; Electronics -- Periodicals; Electronics; Telecommunication; Periodicals; Periodicals; 621.38205
• DOI: 10.4218/etrij.16.2515.0010
• Languages: English
• ISSNs: 1225-6463

Abstract

Abstract : We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second‐order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal‐shape half‐delayed return‐to‐zero feedback DAC eliminates the loop‐delay compensation circuitry and improves pulse‐delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm 2 and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure‐of‐merit of the modulator is 191 fJ/conversion‐step.