A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18‐μm SOI CMOS Technology. Issue 4 (30th August 2013)

• Record Type: Journal Article
• Authors: Cho, Moon‐Kyu; Kim, Jeong‐Geun; Baek, Donghyun
• Is Part Of: ETRI journal. Volume 35:Issue 4(2013)
• Page Start: 638
• Page End: 643
• Publication Date: 2013-08-30
• Subjects: Wideband, phased array antenna, low phase error, SOI, digital step attenuator, SPDT, DPDT switch; Telecommunication -- Periodicals; Electronics -- Periodicals; Electronics; Telecommunication; Periodicals; Periodicals; 621.38205
• DOI: 10.4218/etrij.13.0112.0534
• Languages: English
• ISSNs: 1225-6463

Abstract

Abstract : This paper presents a 5‐bit digital step attenuator (DSA) using a commercial 0.18‐μm silicon‐on‐insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T‐type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is 0.93 mm × 0.68 mm, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC‐to‐20‐GHz SOI DSA.