Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. (April 2018)

• Record Type: Journal Article
• Authors: Amini-Valashani, Majid; Ayat, Mehdi; Mirzakuchaki, Sattar
• Is Part Of: Microelectronics journal. Volume 74(2018)
• Page Start: 49
• Page End: 59
• Publication Date: 2018-04
• Subjects: Arithmetic -- XOR-XNOR cell -- Full adder -- Hybrid design scheme -- Low-power; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.01.018
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18 μm CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%–74% and 35%–81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP.