A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE. (16th August 2017)

• Record Type: Journal Article
• Authors: Samadpoor Rikan, Behnam; Abbasizadeh, Hamed; Cho, Sung‐Hun; Kim, Sang‐Yun; Ali, Imran; Kim, SungJin; Lee, DongSoo; Pu, YoungGun; Lee, MinJae; Hwang, KeumCheol; Yang, Youngoo; Lee, Kang‐Yoon
• Is Part Of: International journal of circuit theory and applications. Volume 46:Number 3(2018)
• Page Start: 375
• Page End: 383
• Publication Date: 2017-08-16
• Subjects: ADC -- segmented DAC -- splitting capacitor -- successive approximation -- thermometer code; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2388
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to "high" and the other one to "low". The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm. Abstract : This paper presents a 6‐bit 4 MS/s successive approximation register analog‐to‐digital converter in which new switching is applied in segmented digital‐to‐analog converter. This structure achieves high energy efficiency by avoiding the requirement of common mode voltage and skipping some of the unnecessary conversion steps in a VCM ‐based successive approximation register analog‐to‐digital converter. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to "high" and the other one to "low". Silicon fabrication and measurement results are presented for this structure.