Using the Intel Many Integrated Core to accelerate graph traversal. (August 2014)

• Record Type: Journal Article
• Authors: Gao, Tao; Lu, Yutong; Zhang, Baida; Suo, Guang
• Is Part Of: International journal of high performance computing applications. Volume 28:Number 3(2014:Autumn)
• Page Start: 255
• Page End: 266
• Publication Date: 2014-08
• Subjects: Many Integrated Core -- MIC -- breadth first search -- BFS -- graph traversal -- heterogeneous computing -- Graph 500; High performance computing -- Periodicals; Supercomputers -- Periodicals; 004.1105
• DOI: 10.1177/1094342014524240
• Languages: English
• ISSNs: 1094-3420

Abstract

Data-intensive applications have drawn more and more attention in the last few years. The basic graph traversal algorithm, the breadth-first search (BFS), a typical data-intensive application, is widely used and the Graph 500 benchmark uses it to rank the performance of supercomputers. The Intel Many Integrated Core (MIC) architecture, which is designed for highly parallel computing, has not been fully evaluated for graph traversal. In this paper, we discuss how to use the MIC to accelerate the BFS. We present some optimizations for native BFS algorithms and develop a heterogeneous BFS algorithm. For the native BFS algorithm, we mainly discuss how to exploit many cores and wide-vector processing units. The performance of our optimized native BFS implementation is 5.3 times that of the highest published performance for graphics processing units (GPU). For the heterogeneous BFS algorithm, the performance of the general processing unit (CPU) and MIC cooperative computing can gain an increase in speed of approximately 1.4 times than that of a CPU for graphs with 2M vertices. This work is valuable for using a MIC to accelerate the BFS. It is also a general guidance for a MIC used for data-intensive applications.