A low power and low phase-noise 91~96 GHz VCO in 90 nm CMOS. Issue 6 (3rd June 2018)

• Record Type: Journal Article
• Authors: Lin, Yo-Sheng; Lan, Kai-Siang; Chuang, Ming-Yuan; Lin, Yu-Ching
• Is Part Of: International journal of electronics. Volume 105:Issue 6(2018)
• Page Start: 1063
• Page End: 1077
• Publication Date: 2018-06-03
• Subjects: CMOS -- VCO -- tuning range -- LC network -- negative capacitance -- series peaking -- output power -- phase noise; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2018.1426116
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin ) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of −188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm 2, i.e. 0.315 mm 2 .