A RISC architecture for 2DLNS-based signal processing. (1st January 2011)

• Record Type: Journal Article
• Authors: Azarmehr, M.; Muscedere, R.
• Is Part Of: International journal of high performance systems architecture. Volume 3:Number 2/3(2011)
• Page Start: 149
• Page End: 156
• Publication Date: 2011-01-01
• Subjects: MDLNS representation -- processor -- reduced instruction set computer -- RISC -- CPU -- multiplication -- FIR filter -- multiply and accumulation -- MAC -- filterbank -- digital signal processing -- DSP; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• DOI: 10.1504/IJHPSA.2011.040467
• Languages: English
• ISSNs: 1751-6528

Abstract

The multi-dimensional logarithmic number system (MDLNS) provides a reduction in the size of the number representation and promises a lower cost realisation of arithmetic operations. The non-linear nature of the representation and independency of the parallel-based computations combined with multi-digit extensions of the MDLNS representations along with simplified arithmetic operations, make MDLNS suitable for some multiplication intensive DSP applications. The work presented in this paper is the design and implementation of a 2DLNS-based processor architecture. This CPU takes advantage of a relatively simple architecture and a well designed organisation which greatly improves the implementation of many DSP algorithms. An assembly programme is also written to implement a 2DLNS-based filterbank architecture. This implementation demonstrates the efficiency and ease of use of 2DLNS CPU in real applications.