A hardware architecture for subtractive clustering. (1st January 2011)

• Record Type: Journal Article
• Authors: Farias, Marcos Santana; Nedjah, Nadia; de Macedo Mourelle, Luiza
• Is Part Of: International journal of high performance systems architecture. Volume 3:Number 2/3(2011)
• Page Start: 167
• Page End: 173
• Publication Date: 2011-01-01
• Subjects: subtractive clustering -- SC -- reconfigurable hardware -- data classification; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• DOI: 10.1504/IJHPSA.2011.040469
• Languages: English
• ISSNs: 1751-6528

Abstract

Clustering algorithms are used extensively to organise and categorise abundant data. This paper describes the implementation of subtractive clustering algorithm in hardware. The solution developed in this paper seeks a hardware implementation to automatic and fast identification of cluster centres. This hardware proposed is generic so it can be used in any data classification problems, omnipresent in identification systems.