A scheduling approach for distributed resource architectures with scarce communication resources. (1st January 2011)

• Record Type: Journal Article
• Authors: Hatanaka, Akira; Bagherzadeh, Nader
• Is Part Of: International journal of high performance systems architecture. Volume 3:Number 1(2011)
• Page Start: 12
• Page End: 22
• Publication Date: 2011-01-01
• Subjects: distributed resource -- compiler -- scheduling -- interconnect -- multi-core -- instruction-level parallelism; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• DOI: 10.1504/IJHPSA.2011.038054
• Languages: English
• ISSNs: 1751-6528

Abstract

Advances in semiconductor fabrication technology will continue to enable exponential increase in the number of transistors available. However, conventional architectures, such as superscalars or VLIWs, will not be able to use the abundant on-chip resources efficiently to achieve high performance because of their inherent lack of scalability. In order to overcome the deficiencies of conventional architectures, architects have come up with a new breed of processors that have distributed resources interconnected via sophisticated networks. Although these processors have the potential of achieving higher performance and being more power efficient than conventional processors, the distributed resources make it difficult to write a compiler that generates a high quality schedule for an application. In this paper, we propose a scheduling approach targeted for such distributed resource architectures. Our approach simultaneously places and schedules an operation and routes communications between consumer and producer operations. We introduce techniques to use the scarce interconnect resources efficiently and empirically to show that they contribute to speeding up applications. In addition, we present a simple yet flexible way to describe the target architecture and generate data structures used for scheduling that represents the interconnect structure of the target architecture.