A networks-on-chip emulation/verification framework. (1st January 2011)

• Record Type: Journal Article
• Authors: Liu, Peng; Liu, Yangfan; Xia, Bingjie; Xiang, Chunchang; Wang, Xiaohang; Wu, Kejun; Wang, Weidong; Yao, Qingdong
• Is Part Of: International journal of high performance systems architecture. Volume 3:Number 1(2011)
• Page Start: 2
• Page End: 11
• Publication Date: 2011-01-01
• Subjects: networks-on-chip -- NoC -- router -- field programmable gate array -- FPGA -- emulation -- on-chip interconnection; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• DOI: 10.1504/IJHPSA.2011.038053
• Languages: English
• ISSNs: 1751-6528

Abstract

The emulation and functional validation are essential to the assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection network architectures. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy and decrease the usage of the resources of field programmable gate array.