Study on nanoparticles embedded multilayer gate dielectric MOS non-volatile memory devices. (1st January 2014)

• Record Type: Journal Article
• Authors: Sengupta, Amretashis; Sarkar, Chandan Kumar
• Is Part Of: International journal of nanotechnology. Volume 11:Number 12(2014)
• Page Start: 1073
• Page End: 1080
• Publication Date: 2014-01-01
• Subjects: MOS -- multilayer gate -- nanoparticles -- Fowler-Nordheim tunnelling.; 620.505
• DOI: 10.1504/IJNT.2014.065133
• Languages: English
• ISSNs: 1475-7435

Abstract

Here, we present a computational study on stacked multilayer nanoparticles embedded gate dielectric MOS non-volatile memory devices. Two device structures, one with a pure SiO 2 tunnel oxide and other with a stacked HfO 2 -SiO 2 tunnel oxide were compared. The Au nanocrystals were assumed embedded in a Si 3 N 4 layer. The electrical parameters of the composite multilayer were evaluated using Maxwell-Garnett theory and virtual crystal approximation. From the WKB approximation, the direct and the Fowler-Nordheim tunnelling currents were evaluated, and subsequently the I-V characteristics and the flatband voltage shifts were also simulated. The flatband shift simulations were compared with recent experimental results.