Design and Evaluation of Binary-Tree Based Scalable 2D and 3D Network-on-Chip Architecture. Issue 4 (2nd October 2017)

• Record Type: Journal Article
• Authors: Ansari, Mohammad Rashid; Ansari, Abdul Quaiyum; Khan, Mohammad Ayoub
• Is Part Of: Smart science. Volume 5:Issue 4(2017)
• Page Start: 194
• Page End: 198
• Publication Date: 2017-10-02
• Subjects: 3D network-on-chip -- network topology -- 3D torus -- Multiprocessor system-on-chip (MPSoC)
• DOI: 10.1080/23080477.2017.1383078
• Languages: English
• ISSNs: 2308-0477

Abstract

Abstract: Network-on-Chip (NoC) has been developed as a most prevailing innovation in the paradigm of communication-centric technology. It solves the limitations of bus-based systems, with the incorporation of 3D IC technology, and it reduces packaging density and improves performance of Multiprocessor System-on-Chip. There is need of suitable NoC topology for these applications and desired performances. This paper proposes a scalable binary tree-based topology for 2D and 3D NoCs. The average degree of the proposed network is reduced around 40% of the torus whereas the diameter also reduced significantly, as compared to other topologies. Abstract :