Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter. (1st February 2017) - Bhattacharya, Rahul; Kumar, Subindu; Biswas, Santosh
Summary: This paper presents a semi‐automated word‐length optimization framework to reduce field‐programmable gate array (FPGA) resource utilization for FPGA‐based pre‐silicon test emulation of analog and mixed signal circuits while achieving the desired accuracy and overcoming long optimization time. Although high‐level behavioral models exist for modeling analog and mixed signal circuits, these comprise many complex differential equations which cannot be realized implicitly using Boolean logic (which is the basic functional block of an FPGA) on an FPGA. So, a more convenient way is explored to map analog circuits into digital domain by converting them into fixed‐point architectures because of its advantage of manipulating data with lower word‐length. To address the loss of accuracy due to finite word‐length effects and limited reconfigurable resources, word‐lengths are optimized under the constraint of given performance metrics. The proposed technique built in MATLAB/Simulink environment with Xilinx System Generator support is illustrated with the help of a case study of a peak‐current‐mode‐controlled buck‐type switching converter implemented on Xilinx Virtex™‐5 FPGA. To illustrate the applicability of this environment for pre‐silicon test development, well‐accepted fault models are emulated with the help of non‐ideal model of a buck converter. The emulation results are seen to be close to that of a post‐fabricated power converter in the presence of faults. Experimental results show that FPGA resource utilization can be reduced significantly while achieving the desired performance accuracy under the constraint of multiple error metrics. Copyright © 2017 John Wiley & Sons, Ltd. Abstract : The aim of this work is to focus on the development of a semi‐automated word‐length optimization algorithm for DC–DC buck converter by reducing field‐programmable gate array (FPGA) resource utilization yet achieving the desired accuracy with minimal optimization time. Apart from this, well‐accepted fault models of a buck converter are also emulated with the help of a non‐ideal model, which shows results that are close to that of a post‐fabricated power converter in the presence of faults.