System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers. (25th January 2017)

• Record Type: Journal Article
• Authors: Hasanzadeh, Mohammad Reza; Abrishamifar, Adib
• Is Part Of: International journal of circuit theory and applications. Volume 45:Number 11(2017:Nov.)
• Page Start: 1576
• Page End: 1599
• Publication Date: 2017-01-25
• Subjects: CT ΔΣ modulator -- Aggressive NTF -- STF Peaking -- CT Loop Filter; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2318
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd. Abstract : Targeting low power and high‐speed applications and based on mathematical approaches, a continuous‐time delta‐sigma modulator that benefits proportional‐integrator element for compensation of excess‐loop‐delay is discussed in this paper. In spite of aggressive noise‐transfer‐function employed in this work, by introducing an extra feedback‐digital‐to‐analog convertors in last integrator, a methodology is developed in which the coefficients of modulator is calculated with almost minimum gain band‐width amplifiers. Also, peaking in signal‐transfer‐function is alleviated using a feed forward capacitor along with proper choosing of modulator's coefficients.