Low energy/delay overhead level shifter for wide‐range voltage conversion. (18th November 2016)

• Record Type: Journal Article
• Authors: Lanuzza, Marco; Crupi, Felice; Rao, Sandro; De Rose, Raffaele; Iannaccone, Giuseppe
• Is Part Of: International journal of circuit theory and applications. Volume 45:Number 11(2017:Nov.)
• Page Start: 1637
• Page End: 1646
• Publication Date: 2016-11-18
• Subjects: level shifter (LS) -- multi‐supply voltage design -- subthreshold operation -- ultra‐low‐voltage interface; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2294
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: Multi‐supply voltage systems on chip have been widely explored for energy‐efficient elaborations. A main challenge of multi‐supply voltage designs is the interfacing of digital signals coming from ultra‐low‐voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay‐efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single‐stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull‐up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage‐level conversion from 0.4 to 1.8 V. Copyright © 2016 John Wiley & Sons, Ltd. Abstract : An energy/delay‐efficient level shifter that is able to convert 100 mV of input voltages to the nominal voltage of 1.8 V is proposed. Measurements on the test chip, fabricated in 180‐nm CMOS technology, show an average propagation delay of 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage level conversion from 0.4 V up to 1.8 V.