Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. (December 2017)

• Record Type: Journal Article
• Authors: Ključar, Luka; González, Mario; Croes, Kristof; De Wolf, Ingrid; De Messemaeker, Joke; Murdoch, Gayle; Nolmans, Philip; De Vos, Joeri; Bömmels, Jürgen; Beyne, Eric; Tőkei, Zsolt
• Is Part Of: Microelectronics and reliability. Volume 79(2017)
• Page Start: 297
• Page End: 305
• Publication Date: 2017-12
• Subjects: CPI -- BEOL -- Via density -- Passivation thickness -- Crack propagation; Electronic apparatus and appliances -- Reliability -- Periodicals; Miniature electronic equipment -- Periodicals; Appareils électroniques -- Fiabilité -- Périodiques; Équipement électronique miniaturisé -- Périodiques; Electronic apparatus and appliances -- Reliability; Miniature electronic equipment; Periodicals; 621.3815
• DOI: 10.1016/j.microrel.2017.07.017
• Languages: English
• ISSNs: 0026-2714

Abstract

Abstract: The influence of via density and passivation thickness on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and advanced copper/low-k processing. The reliability assessment is done using thermal cycling reliability tests, where two dedicated resistance based CPI test structures are analyzed. The data show a correlation between via density and reliability for both passivation modules, where a higher via density reduces the number of failures. In addition, the influence of passivation thickness was determined, where a thinner passivation results in a reduced number of failures. In order to visualize the failures, the interconnect stack was exposed after mechanical removal of the package overmold and Si etching. Cracks were present at the corner of the test chip. Highlights: Improved mechanical reliability with increased via density Improved mechanical reliability with decreased passivation thickness Exposure of the interconnect stack with a combination of mechanical package decapsulation and Si etching Determining the location of crack path at corner test chip using optical microscopy and Scanning Electron Microscopy