BTI mitigation by anti-ageing software patterns. (December 2017) - Abbas, Haider Muhi; Halak, Basel; Zwolinski, Mark
Abstract: This paper presents a time-redundant technique to mitigate Negative and Positive Bias Temperature Instability (NBTI/PBTI) ageing effects on the functional units of a processor. We have analysed the sources and effects of ageing from the device level to the Instruction Set Architecture (ISA) level, and have found that an application may stress the critical paths in such a way that the circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be doubled by applying balanced stress patterns at the software level during the idle time of a processor system. Highlights: A cross-layer analysis has been done to find a technique for CMOS ageing mitigation. A tool to derive the actual BTI stress-recovery ratio from the application level to the logic gate has been developed. An application-level technology-independent mitigation technique is proposed to balance NBTI/PBTI effects. This paper presents a two phase technique to mitigate the NBTI and PBTI ageing effects. After finding the anti-ageing patterns to balance the stress, a program could be executed to propagate these patterns.