System level fault-tolerance core mapping and FPGA-based verification of NoC. (December 2017)

• Record Type: Journal Article
• Authors: Becchu, Naresh Kumar Reddy; Harishchandra, Vasantha Moodabettu; Yernad Balachandra, Nithin Kumar
• Is Part Of: Microelectronics journal. Volume 70(2017)
• Page Start: 16
• Page End: 26
• Publication Date: 2017-12
• Subjects: Network on Chip (NoC) -- Core -- Spare core placement -- Kintex-7 FPGA KC705 evaluation kit; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.09.010
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper proposes a fault-tolerance network on chip (FTNoC) algorithm that incorporates a core graph unit, which is responsible for mapping and scheduling the core graph on the NoC architecture. Fault tolerance unit collects all the fault information from the mapped NoC platform and provides various solutions for different types of fault. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. The proposed FTNoC algorithm was simulated and verified on Kintex-7 (KC705) FPGA board. The results revealed a reduction in area, power consumption and performance improvement compared with previous state-of-the art works.