An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. (December 2017)

• Record Type: Journal Article
• Authors: Chung, Ching-Che; Hou, Chi-Yu
• Is Part Of: Microelectronics journal. Volume 70(2017)
• Page Start: 63
• Page End: 71
• Publication Date: 2017-12
• Subjects: All-digital delay-locked loop -- Digitally controlled delay line -- Clock synchronization -- Clock distribution -- De-skew -- Through-silicon-via (TSV) -- 3-D IC -- 3-D integration; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.10.008
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In a system on a chip (SoC), there are several long global wires that typically limit the maximum SoC clock speed. Therefore, through-silicon via (TSV) technology has been proposed to shorten the length of the global wires. However, the TSV delay variation phenomenon created during the manufacturing process may prevent SoC systems from working properly. This TSV delay variation problem affects data transmission between dies. In this paper, we present an all-digital delay-locked loop (ADDLL) architecture to synchronize clock signals between two dies. We implement the proposed ADDLL in TSMC 90-nm CMOS process with standard cells, which can tolerate process, voltage, and temperature (PVT) variations. In addition, the ADDLL architecture can overcome the TSV delay variation problem using only a single TSV channel. The proposed ADDLL can operate in an input frequency range of 195–960 MHz with a maximum phase error of less than 40.6 ps.