Variability aware transistor stack based regression surrogate models for accurate and efficient statistical leakage estimation. (November 2017)

• Record Type: Journal Article
• Authors: Garg, Lokesh
• Is Part Of: Microelectronics journal. Volume 69(2017)
• Page Start: 1
• Page End: 19
• Publication Date: 2017-11
• Subjects: Standard cells -- Leakage power -- Process variation -- Support Vector Machine -- Probability density function; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.05.015
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, we present highly accurate and very efficient stack based surrogate models for standby (idle-time) statistical leakage estimation of CMOS circuits using sampling based methods. Our aim is to replace SPICE simulation with our proposed surrogate models, which can be used to evaluate samples generated by sampling methods in variation space. Our methodology initiates by first characterizing the leakage of basic transistor stacks and then provides estimate of the leakage of basic gates based on these stacks. Transistor stacks are extracted across various standard cells, which are used to estimate leakage of CMOS gates with different input vector combinations. We develop Support Vector Machine (SVM) regression surrogate models and characterize the transistor stacks of CMOS gates, while accounting the combined effect of process variations in transistor length ( L ), threshold voltage ( V th ), oxide thickness ( T ox ), supply voltage ( 0.6 V − 1.2 V ), temperature ( 0 ° C − 100 ° C ) and width ( 28 nm − 200 nm ), all scalable at the same time. For gates containing parallel transistor stacks, we merge the parallel transistors having identical inputs, which in turn allows us to use precharacterized basic stacks for leakage calculation, thus avoiding generation of new models. Our experiments illustrate that we only require 30 and 26 stack models to predict the subthreshold and gate tunneling leakage of 20 different gates across 176 input combinations, instead of characterizing leakage model for each input vector separately. SVM regression models generated in our approach have the ability to predict the leakage with maximum average error of 2.7% in mean ( μ ) and maximum average error of 3.1% in standard deviation ( σ ), both for OAI22 gate. Our results establish that there is on an average 10 × improvement in runtime while estimating the μ and σ of leakage of a gate within 10000 Monte Carlo simulation loop. Our approaches also result into a maximum of 221 × runtime improvement for C6288 ISCAS'85 benchmark circuit. We further develop Sparse SVM models using Support Vector spectrum pruning method, which reduces the runtime of the regression models with negligible increase in the error. Runtime efficiency of 17 × and 323 × is achieved on standard cell library and C6288 benchmark circuit respectively using Sparse SVM models. Our models outperform previous models based on analytical equations and Artificial Neural Network in terms of accuracy.