Four‐Bits‐Per‐Cell Operation in an HfO2‐Based Resistive Switching Device. Issue 40 (30th August 2017) - Kim, Gun Hwan; Ju, Hyunsu; Yang, Min Kyu; Lee, Dong Kyu; Choi, Ji Woon; Jang, Jae Hyuck; Lee, Sang Gil; Cha, Ik Su; Park, Bo Keun; Han, Jeong Hwan; Chung, Taek‐Mo; Kim, Kyung Min; et al.
Abstract: The quadruple‐level cell technology is demonstrated in an Au/Al2 O3 /HfO2 /TiN resistance switching memory device using the industry‐standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self‐compliance and gradual set‐switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five‐bits‐per‐cell technology, which can hardly be imagined in NAND flash, whose state‐of‐the‐art multiple‐cell technology is only at three‐level (eight states) to this day. Abstract : The highly reliable controllability of the four‐bit resistive switching (RS) operation is demonstrated via the incremental‐step pulse programming (ISPP) and error checking/correction (ECC) algorithms. Through ISPP/ECC, the desired multilevel‐cell operation can be controlled in spite of the stochastic nature of the RS device. This result shows the RS device can be a high‐performance next‐generation nonvolatile memory or neuromorphic device.