Impact of driver size and interwire parasitics on crosstalk noise and delay. Issue 4 (22nd August 2014)

• Record Type: Journal Article
• Authors: Sharma, Devendra Kumar; Kaushik, Brajesh Kumar; Sharma, R.K.
• Editors: Haupt, TheoC.
• Is Part Of: Journal of engineering, design and technology. Volume 12:Issue 4(2014)
• Publication Date: 2014-08-22
• Subjects: Engineering -- Periodicals; Engineering design -- Periodicals; Industrial design -- Periodicals; Technology -- Periodicals; 620.005
• DOI: 10.1108/JEDT-08-2012-0036
• Languages: English
• ISSNs: 1726-0531

Abstract

Abstract : Purpose: To study the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. To show the effect of inductance on delay and to carry out its optimization qualitatively. Design/methodology/approach: The interwire parasitics are the primary sources of crosstalk or coupled noise which may lead to critical delays/ logic malfunctions. This paper is based on simulating a pair of distributed RLC interconnects coupled capacitively and inductively for measurements of crosstalk noise/ delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise / delay are observed through SPICE simulations for different switching patterns.. Furthermore, the analysis of inductive effect on propagation delay as function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13µm, 1.5V technology node. Findings: This paper observes the contradictory effects of coupling parasitics on wire propagation delay, however, the effect on peak noise is of different kind. Further, this paper shows that the driver size exhibit opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance, thus, the optimization of delay is carried out. Originality/value: The effects of driver sizing and inter wire parasitics are analyzed though simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing VLSI interconnects.