Statistical soft error rate estimation of combinational circuits using Bayesian networks. Issue 5 (5th September 2016)

• Record Type: Journal Article
• Authors: Sabet, M. Amin; Ghavami, Behnam
• Is Part Of: Compel. Volume 35:Issue 5(2016)
• Page Start: 1760
• Page End: 1773
• Publication Date: 2016-09-05
• Subjects: Reliability -- Statistical analysis -- CAD -- Circuit analysis -- Fault analysis -- Bayesian network -- Single event transient (SET) -- Soft error -- Process variation; Electrical engineering -- Data Processing -- Periodicals; Electrical engineering -- Mathematics -- Periodicals; Electrical engineering -- Periodicals; Electronics -- Data Processing -- Periodicals; Electronics -- Mathematics -- Periodicals; 621.3
• DOI: 10.1108/COMPEL-09-2015-0317
• Languages: English
• ISSNs: 0332-1649

Abstract

Abstract : Purpose: With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach: In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings: Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value: The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.