UVM-powered hardware/software co-verification. Issue 6 (18th August 2017)

• Record Type: Journal Article
• Authors: Birla, Shilpi; Sharma, Shikha; Shukla, Neeraj Kr.
• Is Part Of: Journal of information & optimization sciences. Volume 38:Issue 6(2017)
• Page Start: 945
• Page End: 952
• Publication Date: 2017-08-18
• Subjects: Co-verification -- Emulator -- QEMU -- Software Driver -- UVM -- vlang -- vlang scheduler; 68U20; Electronic data processing -- Periodicals; Information science -- Periodicals; Mathematical optimization -- Periodicals; 519.6
• DOI: 10.1080/02522667.2017.1372141
• Languages: English
• ISSNs: 0252-2667

Abstract

Abstract: In traditional verification environment, hardware and software involve isolated design and verification. Due to the demise of Moore's law, the processor's frequency is no longer increasing. This demise of Moore's law and time-to-market pressures drive the wave of new technology where hardware and software are tightly integrated. This is done in order to increase the speed of computation. Moreover, in domains like Data Analytics, data has to be processed in real time and that too at low latency. Solarflare's Application On-load Engine (AOE) represents a platform where an FPGA processing engine integrates with a low latency server for applications that require real time and low latency of data processing. This is where co-verification provides a solution for integration of hardware and software. Universal Verification Methodology (UVM) doesn't support co-verification and uses Direct Programming Interface (DPI) for co-simulation. Vlang, which is built on the top of D, a systems programming language, has complete implementation of UVM version 1.2. In co-verification, emulation of software is run along with the hardware verification where, software is emulated separately on Instruction Set Simulator (ISS).