A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis, equalization, and slew rate control. (13th November 2016)

• Record Type: Journal Article
• Authors: Jawed, Syed Arsalan; Asghar, Ali; Khan, Khubaib; Abbasi, Shahbaz; Naveed, Muhammad; Siddiqi, Yasir; Siddiqi, Waqas
• Is Part Of: International journal of circuit theory and applications. Volume 45:Number 10(2017:Oct.)
• Page Start: 1369
• Page End: 1381
• Publication Date: 2016-11-13
• Subjects: LVDS transceiver -- voltage‐mode driver -- low‐power receiver -- pre‐emphasis -- equalization -- slew rate control -- 150‐nm CMOS -- domain shifter; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2289
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd. Abstract : A full‐duplex low‐voltage differential signaling transceiver with configurable pre‐emphasis, equalization, and slew rate control is presented. The fabricated design in 150‐nm complementary metal–oxide–semiconductor occupies an area of 400 × 400μm. The measurement results at 2 Gbps for a 4‐in microstrip and a 10‐m twisted pair cable show 30 and 180 ps of total jitter, respectively. The transmitter consumes 17 mW/2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps.