Clustering based power optimization of digital circuits for FPGAs. Issue 6 (18th August 2017)

• Record Type: Journal Article
• Authors: Verma, Gaurav; Dabas, Chetna; Goel, Ashish; Kumar, Manish; Khare, Vijay
• Is Part Of: Journal of information & optimization sciences. Volume 38:Issue 6(2017)
• Page Start: 1029
• Page End: 1037
• Publication Date: 2017-08-18
• Subjects: K-means -- Xpower -- Slice -- I/O -- FPGAs -- Clustering -- Optimization; 94C99; Electronic data processing -- Periodicals; Information science -- Periodicals; Mathematical optimization -- Periodicals; 519.6
• DOI: 10.1080/02522667.2017.1372154
• Languages: English
• ISSNs: 0252-2667

Abstract

Abstract: The high performance of FPGAs is always the centre of attraction for developing real time embedded devices. But due to their complex circuitry the matter of increasing power utilization can never be ignored. The matter of increasing power utilization in FPGAs is not new and has been addressed in the literature by the researchers previously. Various power efficient models and techniques have been proposed by researchers in last few decades. This paper proposes a new statistical (regression based) power estimation model targeted for low power applications. Around 30 digital circuits have been synthesized using Xilinx Synthesis Tool and power is visualized using Xpower Analyzer and estimated using a power estimation model. The proposed power estimation model shows large deviation in estimating power of some of the digital circuits modelled with power reduction technique. So, this paper also applies k-means clustering algorithm on the parameters obtained after synthesis and power analysis for identifying different types of digital circuits grouped into different clusters. The result shows a good circuit clustering differentiation and it helps in improving the proposed model by reducing the estimation error.