Performance analysis of network-on-chip topologies. Issue 6 (18th August 2017)

• Record Type: Journal Article
• Authors: Kumar, Ana; Tyagi, Shivam; Jha, C. K.
• Is Part Of: Journal of information & optimization sciences. Volume 38:Issue 6(2017)
• Page Start: 989
• Page End: 997
• Publication Date: 2017-08-18
• Subjects: Network-on-chip -- 3D -- 2D -- topologies; 68M12; Electronic data processing -- Periodicals; Information science -- Periodicals; Mathematical optimization -- Periodicals; 519.6
• DOI: 10.1080/02522667.2017.1372145
• Languages: English
• ISSNs: 0252-2667

Abstract

Abstract: Network on chip architecture provides a way to design complex integrated circuits with an objective to reduce connection issues, design productivity, and energy utilization. Network performance of a network is calculated by various factors but throughput is the most dominant characteristic for measuring network performance. So, this work includes investigation of various NoC topologies and analysis is done on basis of average throughput and average latency for ensuring network performance.