A 0.3 V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors. (October 2017)

• Record Type: Journal Article
• Authors: Guo, Wei; Zhu, Zhangming
• Is Part Of: Microelectronics journal. Volume 68(2017)
• Page Start: 44
• Page End: 54
• Publication Date: 2017-10
• Subjects: SAR ADC -- Low voltage -- Low power -- Bulk-driven -- Bootstrapped -- Linearity; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.09.001
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: An 8-bit 10 kS/s 0.3 V ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC merged switching scheme reducing the switch energy by 98.4% compared with conventional switching architecture, the energy consumption of the SAR ADC is decreased drastically. Furthermore, a presented double-bootstrapped switch with leakage reduction technologies improves sampling linearity under 0.3 V. In addition, to relieve non-linearity, boost technique is introduced in digital-to-analog converter (DAC) driving switch. The proposed ADC has been fabricated in 180 nm 1.8 V CMOS process. The measurement results show that effective number of bits (ENOB) of the ADC is 7.21 bit at the Nyquist input frequency and 0.3 V supply voltage, achieving a figure-of-merit (FOM) of 8.9 fJ/conversion-step. The chip area is 0.084 mm 2 .