A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer. (October 2017)

• Record Type: Journal Article
• Authors: Elmiligi, Haytham; Sallam, Mohamed; El-Kharashi, M. Watheq
• Is Part Of: Microelectronics journal. Volume 68(2017)
• Page Start: 55
• Page End: 68
• Publication Date: 2017-10
• Subjects: Networks-on-Chips -- Connection-Then-Credit -- End-to-end protocol -- Credit-based flow control -- Network-interface -- Message-dependent-deadlock -- NoC implementation -- Performance evaluation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.08.012
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper discusses the implementation details of a complete NoC physical layer, basically, the Networks-on-Chip (NoC) routers, links and interfaces. A cycle-accurate RTL design details of complete NoC using a mesh-topology is presented with a special attention to the design of the NoC interface. The proposed implementation provides a complete end-to-end solution for an NoC system in a modular architecture, along with its advanced verification environment, to serve as a development and test platform for future NoC research. The paper also analyzes the performance of the Connection-Then-Credit (CTC) protocol and compares it to the conventional Credit-based (CB) protocol using standard traffic patterns, as well as its post-synthesis implementation results using TSMC 40 nm low-power CMOS technology. Through the addition of a low-power controller to the CTC-based NoC interfaces, our experimental results show a significant efficiency improvement in terms of power-savings, latency and area overhead. The CTC implementation achieved 21.46% saving in power consumption for the VOPD benchmark. In terms of gate-count, the CTC implementation of VOPD, MPEG, and MWD benchmarks achieved 14.40%, 34.05%, and 7.44% less gate counts, respectively.