Triple transistor based fault tolerance for resource constrained applications. (October 2017)

• Record Type: Journal Article
• Authors: Mukherjee, Atin; Dhar, Anindya Sundar
• Is Part Of: Microelectronics journal. Volume 68(2017)
• Page Start: 1
• Page End: 6
• Publication Date: 2017-10
• Subjects: Triple transistor method -- Transistor level redundancy -- Fault tolerance -- Reliability -- Resource constrained; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.08.005
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Fault tolerance has become essential for safety-critical applications like avionics, space, defense, automotive, bio-medical etc., where redundancy must be added to increase the systems' reliability. Incorporation of fault tolerance costs for extra hardware, time and power overhead that limits the use of existing fault tolerant methods in resource constrained applications like satellite, aircraft, surgical equipment, railway, motor vehicles etc. In this paper, we propose a new fault tolerant triple transistor (TT) method, which requires much lesser area overhead compared to the existing methods making it suitable in providing good reliable solutions for various resource constrained applications. In the TT method, redundancy has been added at the transistor level assuring good fault coverage. Theoretical as well as extensive simulation results have been provided to compare our new method with the existing ones and to highlight the advantages and disadvantages of the same.