A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector. (September 2017)

• Record Type: Journal Article
• Authors: Huang, Qiwei; Zhan, Chenchang; Burm, Jinwook
• Is Part Of: Microelectronics journal. Volume 67(2017)
• Page Start: 19
• Page End: 24
• Publication Date: 2017-09
• Subjects: ADPLL -- Digital phase-locked loop (DPLL) -- Bang-bang phase detector -- DCO -- Frequency synthesis -- TDC-less; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.07.004
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD. The MOBBPD can be implemented simply while achieving the merits of both time-to-digital converter (TDC) and bang-bang phase detector (BBPD). The digital PLL's locking time can be reduced due to the multi-output comparing with the classical digital PLL's with standard BBPD. In order to further shorten the loop locking time, we propose to reuse the MSBs, which are trigged at the early stage of locking acquisition, such that the phase difference can quickly decrease. Because of its simple structure, the proposed DPLL can be designed without much effort. The prototype DPLL is fabricated in a standard 0.18-μm CMOS process. The measurement results show that the output clock frequency ranges from 0.768 to 1.344 GHz. The total measured power consumption is 4.7 mW and the measured locking speed is around 40 times faster than a typical design without reusing the MSBs at 1.024 GHz.