An efficient hardware architecture of CAVLC encoder based on stream processing. (September 2017)

• Record Type: Journal Article
• Authors: Orlandić, Milica; Svarstad, Kjetil
• Is Part Of: Microelectronics journal. Volume 67(2017)
• Page Start: 43
• Page End: 49
• Publication Date: 2017-09
• Subjects: H.264/AVC -- Entropy encoding -- CAVLC -- FPGA -- Bitstream packing -- Hardware implementation.; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.07.013
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The paper presents an efficient implementation of Context-Adaptive Variable Length Coding (CAVLC) entropy encoder in H.264/AVC standard. The architecture is designed with a parallel structure targeting real-time video compression. The intensive memory access demand in the syntax element coding stage is lowered by using the proposed arithmetic table elimination technique. The packing stage implementation is interleaved with syntax element generation stage and includes fast methods for syntax elements concatenation. The register update method performs concatenation of the bitstream of previously processed sub-blocks and the syntax codewords of the currently processed sub-block. The CAVLC encoder processes 4 × 4 sub-block coefficients in parallel, introducing the initial latency of 12 clock cycles, after which the full pipeline of the data encoding on the sub-block level is performed, and 16 residuals are processed at each clock cycle. The achieved high throughput allows the encoding core to perform real-time processing of 8 K UHD (4320 p) video sequences with a frame rate of 30 frames/s.