Soft error tolerant design of combinational circuits based on a local logic substitution scheme. (September 2017)

• Record Type: Journal Article
• Authors: Rohanipoor, Mohammad Reza; Ghavami, Behnam; Raji, Mohsen
• Is Part Of: Microelectronics journal. Volume 67(2017)
• Page Start: 143
• Page End: 154
• Publication Date: 2017-09
• Subjects: Soft error -- Soft Error Rate (SER) -- Combinational circuit -- Partitioning -- Logical masking -- Sub-circuit; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.08.006
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one; where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8× faster compared to simulation based method [6].