Bandwidth enlargement of CMOS TIA using on-chip T-network for patient diagnosis in biomedical application. (September 2017)

• Record Type: Journal Article
• Authors: Roy, Gunjan Mittal; Kumar, Sandeep; Kanuajia, Binod Kumar; song, Hanjung
• Is Part Of: Microelectronics journal. Volume 67(2017)
• Page Start: 82
• Page End: 87
• Publication Date: 2017-09
• Subjects: T-network -- Trans-impedance amplifier -- Complementary metal oxide semiconductor (CMOS) -- Optical receiver; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2017.08.003
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This work concerns on CMOS based trans-impedance amplifier (TIA) where enhancing the bandwidth by using optimized on-chip T-network for biomedical diagnosis applications.The proposed TIA consists of inductive peaking components as an input stage, distributed amplifier with feedback loop as middle stage while output as T-network. The proposed TIA with T-network achieves much wide band operation within range of 4.8–19.6 GHz. As compared to conventional TIA, additional trans-impedance bandwidth of 1.4 GHz in the lower band while 9.1 GHz in higher band are able to achieve for the proposed design.The proposed architectures are implemented into ADS platform using commercial 65 nm TSMC process.With this proposed technique, TIA also succeeds lower bit error rate (BER) for high speed data transmission in optical receiver i.e. beneficial towards the biomedical diagnosis. Chip fabrication of proposed TIA consuming less power of 10.8 mW from the power supply of 1.6 V. Measured and simulated data exhibits a wide bandwidth operation with trans-impedance gain of 55dBΩand made good correlation with each other. Moreover, experimental BER demonstrates less than 10 –11 by providing pseudorandom bit sequence at 6–11 Gb/s within desired band of operation in TIA. The optimized on-chip T-network occupies only 10% of the whole chip area of 0.4 mm 2 .