A novel trench SOI LDMOS with a dual floating vertical field plate. (September 2017) - Cheng, Kun; Hu, Shengdong; Lei, Jianmei; Yuan, Qi; Jiang, Yuyu; Huang, Ye; Yang, Dong; Lin, Zhi; Zhou, Xichuan; Tang, Fang
Abstract: A novel trench SOI LDMOS with a dual floating vertical field plate structure (DFVFPT SOI) is proposed in this paper. A dual floating vertical plate (DFVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI). The DFVFP modulates the distribution of the electric field in the drift region especially the trench surface region, which enhances the internal electric field and effectively prevents premature breakdown, thus increasing the breakdown voltage (BV). At the same time, the doping concentration of the drift region ( N d ) is increased because of the assistant depletion effect of DFVFP and a lower specific on-resistance ( R on, sp ) is therefore obtained. Compared with the CT SOI, the R on, sp of the FVFPT SOI can be reduced by more than 35% when its BV can be increased by 27%, and the figure-of-merit (FOM) is enhanced by 145%. Compared with the several structures proposed before, the DFVFPT SOI better improves the tradeoff between BV and R on, sp . Highlights: A novel SOI trench LDMOS with dual floating vertical field plate is proposed. The influences of structure parameters on the performances are investigated. A BV of 238 V and a R on, sp of 1.5 mΩ cm 2 are realized. Figure-of-merit of the proposed structure is enhanced by 145%. A significantly optimized dependence of R on, sp on V B is obtained.