A high fault coverage test approach for communication channels in network on chip. (August 2017) - Aghaei, Babak
Abstract: This paper proposes a new high fault coverage test approach for short faults in Network on Chip communication channels. The proposed approach consists of a built in self-test as well as a Packet/flit Comparing Module (PCM) embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, the detection, location, and routing table updating processes are simultaneously carried out after which the test time is minimized. The approach with high scalability leads to 100% test coverage and 89.5% capability of diagnosing faulty channels in one round (two phases). The simulation results show that the approach hardware and time cost is optimized compared with the previous methodologies. Highlights: Consists of a BIST as well as a Packet/flit Comparing Module (PCM) embedded in the network adapter and a router, respectively. By creating a test traffic, the PCM can manage to locate the faults. In the first phase, the faults on (NA, R) and in the second phase the short faults on (R, R) bidirectional channels are diagnosed. Carrying out the detection, location, and routing table updating processes simultaneously.